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Synchronous semiconductor memory device having a mode requiring an internal clock signal and a mode not requiring the internal clock signal
Synchronous semiconductor memory device having a mode requiring an internal clock signal and a mode not requiring the internal clock signal
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机译:具有需要内部时钟信号的模式和不需要内部时钟信号的模式的同步半导体存储装置
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摘要
A refresh control circuit of a DLL circuit responds to an auto refresh detection signal AR and a self refresh detection signal SR to inhibit input of clock signals ECLK and RCLK to a phase comparator and to a voltage control delay circuit. The DLL circuit can be stopped in a mode where an internal clock signal is not required to reduce power consumption.
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