Method and system for reducing the jitter in a PLL structure (phase locked loop), characterized by a rational relationship between frequencies of input and output.

摘要

PRESENTS A PLL CONTROL METHOD IN THE FREQUENCY ratio departure and entry is a rational number. It IS DEFINED BY THE PRESENCE OF A CONTROL SYSTEM PROGRAMMABLE DIVIDER FREQUENCY IN THIS PPL. BASED ON THE PHASE ERROR CAUSED BY A COMPARISON OF PHASE it IS CONDUCTED AN ESTIMATE phase error oscillator that obtained a control signal FREQUENCY DIVIDER actuator. PPL THE PLAYER HAS A phase error (ERRFAS) to play the comparator output phase PLL CIRCUIT AND PREDICTOR (PRED) to provide the error oscillator phase. THEREFORE THE PLAYER OF ERROR PHASE CONSISTING AS PREDICTOR ACUMULADORES. SYSTEM CONTROL (CONTR) is supplied with the output of these accumulators and generates the control signal crossover. THE PURPOSE OF CONTROL SYSTEM IS TRANSFORMING fluctuation low frequency output signal jitter PLL IN HIGH FREQUENCY which can be removed easily through suitable filtering of signals.