Low-inductance HTS interconnects and Josephson junctions using slot- defined SNS edge junctions

摘要

A technique for defining the active area of a high-T.sub.c superconductor Josephson junction uses an epitaxial slotted insulator patterned over the edge of the superconductor thin film-insulator bilayer. The superconductor/normal-metal/superconductor edge junction formed between the slotted insulator has a small active area. The counter electrode provided as an interconnect of the junction can therefore be wider than the active area of the edge junction since it can overlap onto the patterned slotted insulator. The use of the slotted insulator enables fabrication of junctions having resistances and critical currents in the desired range for high-T.sub.c superconductor circuits while enabling the use of wide, low inductance interconnects.