Synchronous high speed synchro North ram

摘要

In the burst mode operation of the SDRAM in which only the first address is inputted externally and the subsequent address is generated in the chip, the burst address is directly applied to the register which stores the prefetched data without applying the burst address to the column address buffer, The present invention relates to a synchronous high-speed dynamic random access memory (DRAM), and more particularly, to a high-speed synchronous synchronous DRAM capable of reducing a signal path of a DRAM (SDRAM) A plurality of row and column decoders for selecting the row and the column, and a plurality of row and column decoders for sequentially outputting data of the cells selected by the address during the read operation to the bit lines and the data bus lines, Bit Line Sense Amplifiers and Data And a data output buffer for buffering the data of the data bus line and outputting the buffered data to a global input / output line, the synchronous DRAM comprising: A column address buffer and latch means for generating a signal for controlling operation of the column decoder by a column active signal and a burst address generating means for generating a burst address as much as the burst length programmed in the strong mode register when the burst start address is input A burst length counter means for controlling the operation of the burst length counter means, a buffer control means for temporarily storing data transmitted to the global data input / output line, It characterized in that it comprises a data latch means for transmitting to the output buffer.