schaltungsanordnung for mapping of logical to physical address space prozessoreinheit your accessible address space of a memory

摘要

A circuit arrangement for mapping the logical address space of a processing unit (PU) onto the physical address space of a memory (MM), comprising an interpretation unit (IU) which is connected to the processing unit (PU) via data and control lines (D,C) and which contains a register (BCR) divided into a first register area and into a second register area to be loaded by the processing unit, the interpretation unit (IU) continuously evaluating the logic state of the processing unit (PU), loading the content of the second register area into the first register area in the event of certain logical states and outputting the content of the first register area as address, and comprising a logic unit which is connected to the processing unit (PU), the interpretation unit (IU) and the memory (MM) via address lines (A1, A2, A3) and which forms a total address for the memory (MM) from addresses transferred from the interpretation unit (IU) and the processing unit (PU). IMAGE