System for simultaneously writing back cached data via first bus and transferring cached data to second bus when read request is cached and dirty

摘要

A bus bridge mutually connects a CPU bus to which a CPU and a corresponding cache memory having a write-back scheme are coupled, an I/O bus to which a bus master is coupled, and a main memory which is commonly accessed through the CPU bus or I/O bus. In response to an access request from the bus master to the main memory, a cache snooping section snoops a cache memory to see whether an address in the access request satisfies a cache hit or miss, and data corresponding to the address is dirty or clear. In response to a snooping result by the cache snooping section indicating that the cache hit has occurred and the data is dirty, a write- back control section writes back the data from the cache memory in the main memory. In the case where the access request indicates a read request, a data bypass section directly transfers the data from the cache memory onto the I/O bus while the write-back control section performs writing back. With this processing, data read processing from the main memory need not wait for completion of write- back processing with respect to the main memory. Therefore, even if a cache write-back operation is performed in response to a main memory access request from the bus master, the main memory access operation can be performed at a high speed.