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Tolerant integrated circuit to great manufacturing faults

机译:宽容的集成电路可应对重大的制造错误

摘要

The integrated circuit tolerant of large manufacturing defects comprising a first plurality of first conductors (CO1) made of a first material with relatively low conductivity and each having a plurality of first electrical connection points (CP) arranged along itself and a second corresponding plurality of second conductors (CO2) made of a second material with relatively high conductivity and each having a plurality of second electrical connection points (CP) arranged along itself and said plurality of first points are electrically connected to said plurality of second points respectively in such a manner as to reduce the series resistance of the first conductors and the second conductors (CO2) are interrupted between some second consecutive points (CP) in such a manner as to leave relatively large areas of the integrated circuit not traversed by the second conductors (CO2).
机译:具有大的制造缺陷的集成电路,该集成电路包括由第一材料制成的第一多个第一导体(CO1),该第一材料具有相对较低的电导率,每个第一导体具有沿其自身排列的多个第一电连接点(CP)和对应的多个第二第二导体由具有较高电导率的第二材料制成的导体(CO2),每个导体具有沿其自身布置的多个第二电连接点(CP),并且所述多个第一点分别以如下方式电连接到所述多个第二点:为了减小第一导体的串联电阻,第二导体(CO2)在某些第二连续点(CP)之间被中断,以使得集成电路的较大区域未被第二导体(CO2)穿过。

著录项

  • 公开/公告号EP0704901B1

    专利类型

  • 公开/公告日1999-12-15

    原文格式PDF

  • 申请/专利权人 ST MICROELECTRONICS SRL;

    申请/专利号EP19940830468

  • 发明设计人 MAZZALI STEFANO;

    申请日1994-09-30

  • 分类号H01L23/528;H01L27/115;

  • 国家 EP

  • 入库时间 2022-08-22 01:50:02

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