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Method for making a silicon-on-insulator MOS transistor using a selective SiGe epitaxy

机译:使用选择性SiGe外延制造绝缘体上硅MOS晶体管的方法

摘要

Disclosed is a method for manufacturing a metal-oxide- semiconductor (MOS) device formed in an epitaxial silicon layer on insulator substrate comprising the steps of forming a field oxide layer defined an active region of the MOS device in the silicon layer and forming a gate oxide on the silicon layer; forming a gate electrode on the gate oxide, and self- aligned implanting a dopant of low concentration to form a lightly doped drain region; forming an oxide spacer in both sides of the gate electrode; growing a SiGe epitaxial layer having a lower bandgap than the silicon layer on the portion of the exposed silicon layer; and implanting a dopant of high concentration over the SiGe epitaxial layer to form a highly doped source/drain region. This invention can easily manufacture an SOI MOS device having a low source/drain series resistance and a high breakdown voltage without additional complex processes.
机译:公开了一种用于制造在绝缘体衬底上的外延硅层中形成的金属氧化物半导体(MOS)器件的方法,该方法包括以下步骤:在硅层中形成限定该MOS器件的有源区的场氧化层;以及形成栅极硅层上的氧化物;在栅氧化物上形成栅电极,并自对准注入低浓度的掺杂剂以形成轻掺杂的漏极区;在栅电极的两侧形成氧化物隔离物。在暴露的硅层的该部分上生长具有比硅层低的带隙的SiGe外延层;在所述SiGe外延层上注入高浓度的掺杂剂以形成高掺杂的源极/漏极区。本发明可以容易地制造具有低源极/漏极串联电阻和高击穿电压的SOI MOS器件,而无需额外的复杂工艺。

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