首页> 外国专利> SYNCHRONIZING METHOD FOR DELAY SYNCHRONIZING LOOP, DELAY SYNCHRONIZING LOOP, AND SEMICONDUCTOR DEVICE PROVIDED WITH THE DELAY SYNCHRONIZING LOOP

SYNCHRONIZING METHOD FOR DELAY SYNCHRONIZING LOOP, DELAY SYNCHRONIZING LOOP, AND SEMICONDUCTOR DEVICE PROVIDED WITH THE DELAY SYNCHRONIZING LOOP

机译:延迟同步环,延迟同步环和具有该延迟同步环的半导体装置的同步方法

摘要

PROBLEM TO BE SOLVED: To perform accurate delay synchronizing operation with low power consumption. SOLUTION: In a synchronizing method for a delay synchronizing loop, a phase of an external clock ECK is made coincident with an external clock with a phase of dummy data DDT outputted to the outside synchronizing with an internal clock ICK in which the external clock ECK is delayed by the prescribed delay time by chancing a delay time, delay synchronizing operation generating the internal clock ICK synchronizing with the external clock ECK is performed only when a delay synchronizing command DLC indicating start of delay synchronizing operation is supplied from a CPU not shown in a figure, when the synchronizing command DLC is not supplied, a delay time changed by the time is held.
机译:要解决的问题:以低功耗执行准确的延迟同步操作。解决方案:在用于延迟同步环路的同步方法中,使外部时钟ECK的相位与外部时钟重合,并向外部输出虚拟数据DDT的相位与内部时钟ICK同步,其中外部时钟ECK为通过延迟时间而延迟了规定的延迟时间,仅当从未显示在CPU中的CPU提供了指示延迟同步操作开始的延迟同步命令DLC时,才执行生成与外部时钟ECK同步的内部时钟ICK的延迟同步操作。如图所示,当未提供同步命令DLC时,将保留随时间更改的延迟时间。

著录项

  • 公开/公告号JP2001118385A

    专利类型

  • 公开/公告日2001-04-27

    原文格式PDF

  • 申请/专利权人 NEC CORP;

    申请/专利号JP19990296709

  • 发明设计人 SUZUKI MISAO;

    申请日1999-10-19

  • 分类号G11C11/407;G11C11/413;H03L7/00;

  • 国家 JP

  • 入库时间 2022-08-22 01:28:15

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