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ANTI-FUSE OF THREE-ELECTRODE STRUCTURE AND METHOD FOR MAKING MERGED MEMORY LOGIC(MML) SEMICONDUCTOR DEVICE

机译:三电极结构的反熔丝及制造混合逻辑半导体器件的方法

摘要

PURPOSE: Anti-fuse of three-electrode structure and a method for making a merged memory logic semiconductor device are provided to reduce a substrate occupation area by integrating a method for making an analog capacitor having a high breakdown voltage with a method for making an anti-fuse having a low breakdown voltage as one. CONSTITUTION: The first and second conductive patterns are formed to be separated from each other. The first and second insulation sidewall spacers are formed on sidewalls opposed by the first and second conductive patterns. The third conductive pattern is positioned between the sidewall spacers. The first conductive pattern functions as the first electrode(101b), and the second conductive pattern functions as the second electrode(101c). The third conductive pattern functions as the third electrode(107). Under the condition that the third electrode is at a floating state, a breakdown voltage of the first and second sidewall spacers is applied on the first and second electrodes. Thereby, a substrate occupation area is reduced and thus a production cost is also reduced.
机译:目的:通过将用于制造具有高击穿电压的模拟电容器的方法与用于制造反电极的方法相结合,提供了一种三电极结构的反熔丝以及一种用于制造合并的存储逻辑半导体器件的方法,以减小基板占用面积。 -具有低击穿电压的保险丝。组成:第一和第二导电图案形成为彼此分离。第一绝缘侧壁隔离物和第二绝缘侧壁隔离物形成在与第一导电图案和第二导电图案相对的侧壁上。第三导电图案位于侧壁间隔物之间​​。第一导电图案用作第一电极(101b),第二导电图案用作第二电极(101c)。第三导电图案用作第三电极(107)。在第三电极处于浮置状态的条件下,在第一电极和第二电极上施加第一侧壁间隔物和第二侧壁间隔物的击穿电压。从而,减小了基板占用面积,因此也降低了生产成本。

著录项

  • 公开/公告号KR20010004802A

    专利类型

  • 公开/公告日2001-01-15

    原文格式PDF

  • 申请/专利权人 HYNIX SEMICONDUCTOR INC.;

    申请/专利号KR19990025521

  • 发明设计人 CHO NAM HONG;

    申请日1999-06-29

  • 分类号H01L27/00;

  • 国家 KR

  • 入库时间 2022-08-22 01:14:19

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