Reducing access time on dynamic random access memory by interposing two read cache memories and two write cache memories between the dynamic random access memory and the column decoder

摘要

Two cache memories (A, B) are exclusively used for reading and are connected to a bus (45) and the memory map (2) through ports (52,65). They are also connected to the output (DOUT) by ports (54,58). Two writing cache memories (C,D) receive input (DIN) through ports (64,74) and are connected to the bus (45) by ports (60,70). The writing cache ports are controlled by and gates and place marker registers (80,82)