首页> 外国专利> Basic block oriented trace cache utilizing a basic block sequence buffer to indicate program order of cached basic blocks

Basic block oriented trace cache utilizing a basic block sequence buffer to indicate program order of cached basic blocks

机译:面向基本块的跟踪缓存,利用基本块序列缓冲区指示缓存的基本块的程序顺序

摘要

A cache memory configured to access stored instructions according to basic blocks is disclosed. Basic blocks are natural divisions in instruction streams resulting from branch instructions. The start of a basic block is a target of a branch, and the end is another branch instruction. A microprocessor configured to use a basic block oriented cache may comprise a basic block cache and a basic block sequence buffer. The basic block cache may have a plurality of storage locations configured to store basic blocks. The basic block sequence buffer also has a plurality of storage locations, each configured to store a block sequence entry. The block sequence entry may comprise an address tag and one or more basic block pointers. The address tag corresponds to the fetch address of a particular basic block, and the pointers point to basic blocks that follow the particular basic block in a predicted order. A system using the microprocessor and a method for caching instructions in a block oriented manner rather than conventional power-of-two memory blocks are also disclosed.
机译:公开了一种被配置为根据基本块访问所存储的指令的高速缓冲存储器。基本块是分支指令产生的指令流中的自然划分。基本块的开始是分支的目标,而结束是另一个分支指令。被配置为使用面向基本块的高速缓存的微处理器可以包括基本块高速缓存和基本块序列缓冲器。基本块高速缓存可以具有被配置为存储基本块的多个存储位置。基本块序列缓冲器还具有多个存储位置,每个存储位置被配置为存储块序列条目。块序列条目可以包括地址标签和一个或多个基本块指针。地址标签对应于特定基本块的获取地址,并且指针指向以预测顺序跟随该特定基本块的基本块。还公开了一种使用微处理器的系统和用于以面向块的方式而不是传统的二乘幂存储块来缓存指令的方法。

著录项

  • 公开/公告号US06185675B2

    专利类型

  • 公开/公告日2001-02-06

    原文格式PDF

  • 申请/专利权人

    申请/专利号US09137579

  • 发明设计人 UWE KRANICH;DAVID S. CHRISTIE;

    申请日1998-08-21

  • 分类号G06F93/80;

  • 国家 US

  • 入库时间 2022-08-22 01:07:24

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