Semiconductor memory device having a first source line arranged between a memory cell string and bit lines in the direction crossing the bit lines and a second source line arranged in parallel to the bit lines

摘要

A semiconductor device comprises select gates and control gates of a plurality of memory cells therebetween so that gate members on upper portions of stacked gates may cross element regions. A metal interconnection is disposed parallel to an upper layer of the element region. A source line SL is arranged at intervals of plural bit lines BL. The source line is led to a source line contact through a conductive member composed of a low-resistance metal in the same manner as a bit line contact.