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Fractional-spurs suppression scheme in frequency tracking multi-band fractional-N phase lock loop
Fractional-spurs suppression scheme in frequency tracking multi-band fractional-N phase lock loop
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机译:频率跟踪多频带小数N分频锁相环中的小数杂散抑制方案
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摘要
The present invention discusses fractional compensation timing circuitry (15) to track a VCO output frequency, fO, and provide highly effective error cancellation in a fractional-N PLL synthesizer. This output frequency tracking is used to suppress spurious sidebands, commonly known as spurs, in both fixed-band and multi-band wireless transceiver applications which use fractional-N PLL synthesizers. Some of the critical parameters which benefit from this type of PLL include switching time, phase noise, and reference feed-through.
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机译:本发明讨论了分数补偿定时电路( 15 B>),以跟踪VCO输出频率f O Sub>,并在分数N PLL合成器中提供高效的误差消除。此输出频率跟踪用于抑制使用小数N分频PLL合成器的固定频带和多频带无线收发器应用中的杂散边带(通常称为杂散)。得益于此类PLL的一些关键参数包括开关时间,相位噪声和参考馈通。
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