Layout design manner of transistor optimization manner and the device and the integrated circuit and record the device and the transistor optimization program record media, record the layout design program of the integrated circuit record media, and the integrated circuit

摘要

PROBLEM TO BE SOLVED: To optimize the size of a transistor in combination with the number of turning steps in the design of an integrated circuit. ;SOLUTION: The size of a transistor and the number of turning steps are optimized using a turning model wherein the number of a plurality of turning steps is set to one transistor size. In this turning model, when the lower limit value of the transistor size W is assumbed to be W0 and the height of a layout region is assumed to be H0, the number N of the turning steps can be arbitrarily set in the range of W/H0≤N≤W/W0. By optimizing the size of the transistor along with the number of the turning steps in the range to satisfy a given design constraint using this model, an integrated circuit, which is excellent in the aspects of area and performance, can be designed.;COPYRIGHT: (C)2000,JPO