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Data communications device and associated method for arbitrating access using dynamically programmable arbitration scheme and limits on data transfers

机译:数据通信设备和相关方法,用于使用动态可编程仲裁方案和数据传输限制来仲裁访问

摘要

Data communications device and method for arbitrating access to a system memory of the communications device via a peripheral component interconnect (PCI) bus in a network interface having a memory management unit for managing transmit data transfers from the system memory to a transmit buffer memory, and receive data transfers from a receive buffer memory to the system memory. The memory management unit includes an arbitration block having an arbiter state machine, which receives requests for access to the PCI bus in order to provide the transmission and reception of data, descriptors and status information. The arbiter state machine grants the PCI bus access to a request having a higher priority in accordance with a preset priority scheme. The memory management unit has a transmit transfer control register and a receive transfer control register containing programmable values that limit the maximum number of transmit data transfers and receive data transfers allowed within a single PCI bus mastership period. Also, the transmit and receive transfer control registers contain programmable values that limit the number of allowed transmit data transfers within a single PCI bus mastership period when a request for a receive data transfer is asserted, and limit the number of allowed receive data transfers in a PCI bus mastership period when a request for a transmit data transfer is active. The transfer control values in the transmit and receive transfer control registers are dynamically programmed by a host based on data traffic in the PCI bus. Also, the transmit and receive transfer control register values may be preprogrammed based on the network interface application, for example, whether the network interface is used in a network client or network file server.
机译:数据通信设备和方法,用于仲裁通过网络接口中的外围组件互连(PCI)总线对通信设备的系统存储器的访问,该接口具有用于管理从系统存储器到传输缓冲存储器的传输数据传输的存储器管理单元,以及接收从接收缓冲存储器到系统存储器的数据传输。存储器管理单元包括具有仲裁器状态机的仲裁块,该仲裁器状态机接收访问PCI总线的请求,以便提供数据,描述符和状态信息的发送和接收。仲裁器状态机根据预设的优先级方案将PCI总线访问权限授予优先级更高的请求。存储器管理单元具有一个传输传输控制寄存器和一个接收传输控制寄存器,其中包含可编程值,这些可编程值限制了单个PCI总线主控期内允许的最大传输数据传输和接收数据传输数量。同样,发送和接收传输控制寄存器包含可编程值,这些可编程值在声明了接收数据传输的请求时限制单个PCI总线主控期间内允许的传输数据传输的数量,并限制在一个PCI总线主控期间内允许的接收数据传输的数量。发送数据传输请求处于活动状态时的PCI总线主控期限。主机根据PCI总线中的数据流量对发送和接收传输控制寄存器中的传输控制值进行动态编程。同样,可以基于网络接口应用程序(例如,网络接口是在网络客户端中还是在网络文件服务器中使用)对发送和接收传输控制寄存器值进行预编程。

著录项

  • 公开/公告号US6345345B1

    专利类型

  • 公开/公告日2002-02-05

    原文格式PDF

  • 申请/专利权人 ADVANCED MICRO DEVICES INC.;

    申请/专利号US19990236586

  • 发明设计人 CHING YU;JERRY KUO;

    申请日1999-01-26

  • 分类号G06F131/40;G06F133/60;

  • 国家 US

  • 入库时间 2022-08-22 00:46:29

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