Determination of the position of defective memory cells in a memory chip so that they can be replaced by redundant memory cells by provision of self test capability and use of a parallel to serial converter with a buffer memory

摘要

An integrated semiconductor memory with a self test mode has a memory cell field (1) with row and column coders (2, 3) for selection of memory cells from the cell field as well as for read-write access, a test device (7) coupled to the memory cell field so that it can execute its function testing and a buffer memory (11) in which row and column data relating to defective memory cells is stored. Memory chip also has a parallel to serial converter (15) connected between the buffer memory and an input-output interface (16) of the memory for output of test data. The invention also relates to a corresponding test system (18) used with a semiconductor memory (17) that has an input-output interface that allows it to connect to a workstation for redundancy calculations.