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Algorithm and methodology for the polygonalization of sparse circuit schematics
Algorithm and methodology for the polygonalization of sparse circuit schematics
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机译:稀疏电路原理图多边形化的算法和方法
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摘要
An method of creating a physical layout of an integrated circuit. A schematic file (600) is mapped directly to a physical layout using the location of elements and routing of interconnections as specified in the schematic file (600). The method takes advantage of constraints on the schematic design to provide the layout file (675) quickly, without complex routing programs. Design rules violations are anticipated and corrected in some cases. In other cases, the design rule violations are annotated, if the designer intentionally placed them in the design.
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