Variable read/write margin high-performance soft-error tolerant SRAM bit cell
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机译:可变读/写裕量高性能软容错SRAM位单元
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摘要
A single event upset (SEU) tolerant SRAM bit cell for six-transistor (6T), eight-transistor (8T), or multi-port RAM cell configurations fabricated in accordance with 0.18 &mgr;m or smaller CMOS processes. SEU tolerance is achieved without significantly increasing the cell's read and write cycle time and negligible impact on cell stability.
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