Capacitor mismatch independent gain stage for differential pipeline analog to digital converters

摘要

A method and apparatus are arranged for minimizing the effects of capacitor mismatch errors in pipelined analog-to-digital converters (ADC). The virtual elimination of capacitor mismatch effects is achieved without trading comparator-offset margin by an appropriate selection of comparator circuits' reference signals and the inclusion of a plurality of capacitors that are switched into an appropriate feedback position. The appropriate feedback position in the switched capacitor amplifier circuit is determined based on the operating region. For each of k pipeline stage, a method includes: determining an operating region of a sampled analog input signal for a predetermined transfer curve, and computing digital code bits and an improved residue signal for this stage based on the determined operating region, and then computing a final conversion code from the digital code bits of the k pipeline stages.