Semiconductor memory device lowering high frequency system clock signal for the use of operation frequency of address and command and receiving different frequency clock signals, memory module and system having the same

摘要

PURPOSE: A semiconductor memory device is provided to be capable of adjusting an operating frequency of address and command signals although a frequency of a clock signal is increased. CONSTITUTION: A clock buffer(310) receives a clock signal(CLK) on a clock bus to generate internal clock signals(CLK1, CLK2). The clock buffer(310) determines frequencies of the internal clock signals(CLK1, CLK2) in response to a control signal(CTRL) of a controller(350). The controller(350) includes a mode register set, and the control signal(CTRL) is set at power-up of a semiconductor memory device(101). An address buffer(320) receives an address signal in response to the first internal clock signal(CLK1), and a command buffer(330) receives a command signal(CMD) in response to the first internal clock signal(CLK1). A data buffer(340) inputs and outputs data in response to the second internal clock signal(CLK2) whose frequency is identical to that of the clock signal(CLK).