Test pattern generator circuit for use in testing BIST integrated circuits with test data, whereby said circuit incorporates an address exchanger circuit that enables interchanging of low and high address value lines

摘要

Test pattern generator circuit (1) has an address generator circuit (2) for generation of addresses (A1-7) to which the test data is to be addressed. Said circuit comprises low and high value address lines connected to an address exchanger circuit (4) to transfer the generated addresses. The exchanger circuit has output low and high value test address lines and can be controlled by control signals (S1, S2) so that the input low value address line is connected to the high value test address line and vice versa. An Independent claim is made for a method for generation of a test addresses with a test width of at least two address bits, whereby the input address values can be mixed to obtain a test address.