Chip scale package comprises conductive layers formed on upper and lower chip surfaces and electrode surfaces on same side surfaces of conductive layers

摘要

A chip scale package comprises first and second conductive layers formed on an insulating layer and spaced from each other by a designated distance to be connected to each of two terminals; a third conductive layer formed on the second surface of the chip to be connected to the terminal of the second chip surface; and electrode surfaces formed on each of designated side surfaces of the conductive layers. A chip scale package (40) comprises a chip (45) having a first surface provided with two first terminals and an opposite second surface provided with a second terminal; an insulating layer (43) formed on the first surface of the chip except for areas for two terminals; first and second conductive layers (41a, 41b) formed on the insulating layer and spaced from each other by a designated distance to be connected to each of two terminals; a third conductive layer (41c) formed on the second surface of the chip to be connected to the terminal of the second surface of the chip; and electrode surfaces (47a-47c) formed on each of designated side surfaces of the first, second and third conductive layers. Independent claims are also included for the following: (a) a chip scale package assembly comprising a chip scale package; and a printed circuit board (51) comprising at least three connection pads (57a-57c) and circuit patterns connected to the connection pads, wherein the chip scale package is mounted on the printed circuit board so that the electrode surfaces of the chip are attached to each of the connection pads of the printed circuit board; and (b) forming a chip scale package by preparing a wafer including chips; forming an insulating layer on the upper surface of the wafer except for areas for two terminals; forming an upper conductive layer on insulating layer to be connected to each of two terminals of the upper surface of the chip; forming a lower conductive layer on the lower surface of the chip to be connected to the terminal of the lower surface of the chip; first-dicing the wafer so that one side surface of the chip scale package is formed; forming electrode surfaces on side surfaces of the upper and lower conductive layers; dividing the upper conductive layer formed on the insulating layer into two areas connected to each of two terminals; and second-dicing the wafer into package units.