Core parallel embodiment with different optimization characteristics, in order to reduce the dynamic design type.

摘要

The invention to provide a processor having two or more parallel command because for processing of commands. The command path can with a plurality of cores be implemented on a common chip. Commands of the invention, preferably within a bundle of two or more instructions of a common program part process is being processed, and each of the command path, preferably, forms a cluster, in order to process instructions, bundled. Each of the command path has an array of interleaved in time to execution units operating. Initially processing two or more of the parallel instruction paths the same program part process (of one or more bundles) by the same execution units, but with different optimization characteristics, which are set for each path. The evaluation logic monitors the processing of the initially - program part process by the execution units and selects the heuristic, which is defined, which path in guide is. The other instruction paths are then associated with new or with the optimization of characteristics of the guiding command path or with similar optimized characteristics synchronized, in order to other bundles of the program part process to be processed, preferably, the path leading the processing of the initially - subprocess, without being disturbed. In the case of other program part processes, the process can be in the processing of the same bundle by means of a plurality of instruction paths are repeated to the preferred heuristic ..