首页> 外国专利> METHOD FOR ACCELERATING ELECTRONIC COMPONENT POOR PACKAGE RATE, AND METHOD FOR COMPARING ELECTRONIC COMPONENT POOR PACKAGE RATES

METHOD FOR ACCELERATING ELECTRONIC COMPONENT POOR PACKAGE RATE, AND METHOD FOR COMPARING ELECTRONIC COMPONENT POOR PACKAGE RATES

机译:加快电子元件不良率的方法和比较电子元件不良率的方法

摘要

PROBLEM TO BE SOLVED: To provide a method for accelerating electronic component poor package rates for enabling a significant comparative test by intentionally accelerating the occurrence of poor packages, such as tombstones, and to provide a method for comparing electronic component poor package rates.;SOLUTION: Electronic component 2a, and a test board 1a wherein a plurality of land patterns 4 are formed each corresponding to one of the external electrodes 3 built at both ends of the electronic components 2a, are prepared. A conductive bonding material 5 is attached to each land pattern 4 and then the electronic components 2a are arranged, and the test board 1a is subjected to a reflow treatment. These steps are performed at least once, and a plurality of test pieces 9 are obtained, each different from the others concerning at least one out of the electronic component 2a, the land pattern 4, the constituents of the conductive bonding material 5, the position of the electronic component 2a as mounted, and the reflow conditions. A tombstoning rate is determined for each of the test pieces 9, and comparison is established.;COPYRIGHT: (C)2004,JPO&NCIPI
机译:解决的问题:提供一种加速电子元件不良封装率的方法,以通过有意加速不良封装(例如墓碑)的出现来进行显着的比较测试,并提供一种电子元件不良封装率的比较方法。 :准备电子部件2a和测试板1a,其中形成有多个焊盘图案4,每个焊盘图案与在电子部件2a的两端建立的外部电极3之一相对应。将导电接合材料5附着到每个焊盘图案4,然后布置电子部件2a,并且对测试板1a进行回流处理。这些步骤至少进行一次,得到多个测试片9,每个测试片9与电子元件2a中的至少一个,焊盘图案4,导电接合材料5的成分,位置,位置不同。电子元件2a的安装状态,回流条件。确定每个测试件9的墓碑脱落率,并进行比较。;版权所有:(C)2004,JPO&NCIPI

著录项

  • 公开/公告号JP2004247515A

    专利类型

  • 公开/公告日2004-09-02

    原文格式PDF

  • 申请/专利权人 MURATA MFG CO LTD;

    申请/专利号JP20030035722

  • 发明设计人 UTSUNOMIYA ISAMU;

    申请日2003-02-13

  • 分类号H05K3/34;

  • 国家 JP

  • 入库时间 2022-08-21 23:31:18

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