Method and system for short-circuit current modeling in CMOS integrated circuits

摘要

A method and system for short-circuit current modeling in CMOS circuit provides improved accuracy for logic gate power dissipation models in computer-based verification and design tools. The model determines the short circuit current for each complementary pair within a CMOS circuit. Input and output voltage waveforms provided from results of a timing analysis are used to model the behavior one device of the complementary pair. The device is selected as the limiting device (the device transitioning to an off state) from the direction of the logic transition being modeled, which is also the device that is not charging or discharging the output load. Therefore, the current through the selected device can be determined from the input and output waveforms and is equal to the short-circuit current prior to the saturation of the selected device. One or more short-circuit current points can be determined from the model and used to generate a polygonal waveform model of the short-circuit current, or can be used along with the width (period) of the waveform to calculate short-circuit power dissipation directly.