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Branch metric unit duplication for high speed decoder FPGA implementation
Branch metric unit duplication for high speed decoder FPGA implementation
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机译:分支度量单位重复用于高速解码器FPGA实现
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摘要
A branch metric duplication method substantially reduces interconnection delays. The branch metric duplication method is particularly useful to implement a high speed radix-4 Viterbi decoder targeted for FPGA applications.
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