Method of generating timing constraint model of logic circuit, program for generating timing constraint model of logic circuit, and timing-driven layout method of using the timing constraint model

摘要

An STA script input section receives input of an STA script that includes a clock information and a path disconnection information. A path permissible delay time calculator extracts paths that do not have the disconnection information, and calculates a permissible delay time from a starting point to an ending point of each of the paths. A CCS preparing section prepares the timing constraint model of the compatible constraint set that describes the timing constraints of each path, and the disconnection information, for a plurality of groups of information to have no contradiction between the paths extracted and the disconnection information. Finally, a CCS combining unit obtains one compatible constraint set that takes into account operation modes by simply combining the compatible constraint sets output from the CCS preparing section.