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Multichip semiconductor device having a hip with redundancy restoration fuse that affects a redundant memory array
Multichip semiconductor device having a hip with redundancy restoration fuse that affects a redundant memory array
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机译:具有髋部的多芯片半导体器件,该髋部具有影响冗余存储阵列的冗余恢复保险丝
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摘要
A multichip semiconductor device with an improved yield and a reduced inspection cost is provided in which a fuse is provided on a first semiconductor chip while a fuse is not provided on a second semiconductor chip as a rewritable memory, and these chips are connected inside a package. The second semiconductor chip includes redundancy cells to be replaced for defective bits. To produce a post-redundancy-restoration state in which the defective bits are replaced with the redundancy cells before the second semiconductor chip is connected with the first semiconductor chip, the second semiconductor chip includes a restoration state determining circuit and a command decode circuit. The restoration state determining circuit is for storing a redundancy restoration solution for restoring defective bits supplied via a first external input pad. The command decoder circuit controls input from the first external input pad to the restoration state determining circuit according to a signal supplied via a second external input pad.
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