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Multichip semiconductor device having a hip with redundancy restoration fuse that affects a redundant memory array

机译:具有髋部的多芯片半导体器件,该髋部具有影响冗余存储阵列的冗余恢复保险丝

摘要

A multichip semiconductor device with an improved yield and a reduced inspection cost is provided in which a fuse is provided on a first semiconductor chip while a fuse is not provided on a second semiconductor chip as a rewritable memory, and these chips are connected inside a package. The second semiconductor chip includes redundancy cells to be replaced for defective bits. To produce a post-redundancy-restoration state in which the defective bits are replaced with the redundancy cells before the second semiconductor chip is connected with the first semiconductor chip, the second semiconductor chip includes a restoration state determining circuit and a command decode circuit. The restoration state determining circuit is for storing a redundancy restoration solution for restoring defective bits supplied via a first external input pad. The command decoder circuit controls input from the first external input pad to the restoration state determining circuit according to a signal supplied via a second external input pad.
机译:提供了一种具有提高的成品率和降低的检查成本的多芯片半导体器件,其中在第一半导体芯片上提供熔丝,而在第二半导体芯片上不提供熔丝作为可重写存储器,并且这些芯片被连接在封装内。 。第二半导体芯片包括将被替换为缺陷位的冗余单元。为了产生其中在第二半导体芯片与第一半导体芯片连接之前用冗余单元替换缺陷位的冗余后恢复状态,第二半导体芯片包括恢复状态确定电路和命令解码电路。恢复状态确定电路用于存储冗余恢复方案,该冗余恢复方案用于恢复经由第一外部输入焊盘提供的缺陷位。命令解码器电路根据经由第二外部输入焊盘提供的信号来控制从第一外部输入焊盘到恢复状态确定电路的输入。

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