n-1, ..., b0 of input data B as an active bit. Binary data for indicating the bit position S of the active bit is generated as a logarithmic transformation upper bit string DUP (dm-1, ..., dm-p). Here, based on the number of bits n of the input data B, the number of bits p of the logarithmic transformation upper bit string DUP (dm-1, ..., dm-p) is set for the relationship n = 2P. A logarithmic transformation lower bit string generating unit (4) determines a bit string of order lower than the bit position S, having a predetermined number q of bits, out of the bits bn-1, ..., b0 of the input data B. The resultant bit string makes a logarithmic transformation lower bit string DLOW (dm-p-1, ..., d0). Then, logarithmic transformation data D having a total number of p + q bits is generated with the logarithmic transformation upper bit string DUP (dm-1, ..., dm-p) as the integral part of a logarithmic transformation value resulting from the logarithmic transformation of the input data B and the logarithmic transformation lower bit string DLOW (dm-p-1, ..., d0) as the fractional part of the logarithmic transformation value resulting from the logarithmic transformation of the input data B."/> Logarithmic transformer and method of logarithmic transformation
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Logarithmic transformer and method of logarithmic transformation

机译:对数变换器和对数变换方法

摘要

A logarithmic transformer capable of a reduction in circuit scale. A logarithmic transformation upper bit string generating unit (3) detects a highest order bit of logic "1" out of the bits bn-1, ..., b0 of input data B as an active bit. Binary data for indicating the bit position S of the active bit is generated as a logarithmic transformation upper bit string DUP (dm-1, ..., dm-p). Here, based on the number of bits n of the input data B, the number of bits p of the logarithmic transformation upper bit string DUP (dm-1, ..., dm-p) is set for the relationship n = 2P. A logarithmic transformation lower bit string generating unit (4) determines a bit string of order lower than the bit position S, having a predetermined number q of bits, out of the bits bn-1, ..., b0 of the input data B. The resultant bit string makes a logarithmic transformation lower bit string DLOW (dm-p-1, ..., d0). Then, logarithmic transformation data D having a total number of p + q bits is generated with the logarithmic transformation upper bit string DUP (dm-1, ..., dm-p) as the integral part of a logarithmic transformation value resulting from the logarithmic transformation of the input data B and the logarithmic transformation lower bit string DLOW (dm-p-1, ..., d0) as the fractional part of the logarithmic transformation value resulting from the logarithmic transformation of the input data B.
机译:能够减小电路规模的对数变压器。对数变换高位串生成单元(3)从b n-1 ,...,b 0 位中检测逻辑“ 1”的最高位输入数据B的有效位。指示活动位的位位置S的二进制数据作为对数转换高位字符串D UP (d m-1 ,...,d mp )。在此,根据输入数据B的位数n,对数变换高位串D UP (d m-1 ,...的位数p。 ..,d mp )设置为关系n = 2 P 。对数变换低位串生成单元(4)从b n-1 ,...位中确定具有预定数量q个位的比位位置S低阶的位串。 。,b 0 。结果位字符串进行对数转换低位字符串D LOW (d mp-1 , ...,d 0 )。然后,用对数变换高位串D UP (d m-1 ,...,,产生总数为p + q位的对数变换数据D d mp )作为对数转换值的整数部分,该对数转换值由输入数据B的对数转换和对数转换低位字符串D LOW (d mp-1 ,...,d 0 )作为对数变换值的小数部分,该对数变换值是由输入数据B的对数变换得出的。

著录项

  • 公开/公告号EP1385084A1

    专利类型

  • 公开/公告日2004-01-28

    原文格式PDF

  • 申请/专利权人 PIONEER CORPORATION;

    申请/专利号EP20030016797

  • 发明设计人 YAMAMOTO YUJIC/O KAWAGOE KOUJOU;

    申请日2003-07-23

  • 分类号G06F7/556;

  • 国家 EP

  • 入库时间 2022-08-21 22:53:34

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