DELAY COMPENSATION PIPELINE DEVICE IN ACCORDANCE WITH PIPE REGISTERS OF A SEMICONDUCTOR ELEMENT, SPECIALLY RELATED TO OBTAINING A MINIMUM CYCLE TIME WITH A HIGH-SPEED CYCLE TIME, AND INCREASING PRODUCT COMPETITIVENESS

摘要

PURPOSE: A delay compensation pipeline device in accordance with pipe registers of a semiconductor element is provided to non-uniformly locate plural pipe registers between an input end and an output end of a semiconductor element, and to minimize a cycle time of a clock even though each data path delay is not identical, thereby improving an operational speed. CONSTITUTION: Pipe registers are located between an input end(A) and an output end(B) synchronized with an external clock signal, and are positioned at a time 't2' from the output end(B) and at a time 't1' from the input end(A). The first delay circuit(11) receives the external clock signal to delay the received external signal for a certain time, and generates an internal clock signal for synchronizing the pipe registers.