首页> 外国专利> Output circuit and method that inverts the data byte if the number of changed bits compared with the last byte is more than half the total number of bits.

Output circuit and method that inverts the data byte if the number of changed bits compared with the last byte is more than half the total number of bits.

机译:如果与最后一个字节相比更改后的位数大于位数总数的一半,则将数据字节反转的输出电路和方法。

摘要

A data output circuit which outputs data received on an internal bus line onto an external bus line comprises a comparator, an inverter and a controller. The comparator compares data on the external bus line and data to be output received on the internal line. The inverter outputs the inverse of the data received on the internal bus when the number of bits that would be changed exceeds half the total number of bits in a byte and determined by the result output by the comparator. The controller outputs an inversion display signal indicating that the data has or has not been inverted. The circuit may be a control unit. The circuit may comprise an amplifier which amplifies the read data, data latch means for latching data from the amplifier and means for feeding the data to the comparator. The circuit may comprise a clock supply means to supply a clock signal to the data latch and/or the comparator. The control circuit may be arranged to control a plurality of groups, the groups obtained by classifying the internal bus lines into groups.
机译:将内部总线上接收到的数据输出到外部总线上的数据输出电路包括比较器,逆变器和控制器。比较器比较外部总线上的数据和内部总线上要输出的数据。当要更改的位数超过一个字节中位数的一半并且由比较器输出的结果确定时,逆变器将输出内部总线上接收到的数据的逆运算。控制器输出指示数据已经或尚未被反转的反转显示信号。该电路可以是控制单元。该电路可以包括:放大器,其放大读取的数据;数据锁存装置,用于锁存来自放大器的数据;以及用于将数据馈送到比较器的装置。该电路可以包括时钟供应装置,以向数据锁存器和/或比较器供应时钟信号。控制电路可以被布置为控制多个组,这些组通过将内部总线线路分类为组而获得。

著录项

  • 公开/公告号GB2394088A

    专利类型

  • 公开/公告日2004-04-14

    原文格式PDF

  • 申请/专利权人 * NEC CORPORTION;* NEC CORPORATION;

    申请/专利号GB20030019465

  • 发明设计人 KOJI * NAGANAWA;

    申请日2003-08-19

  • 分类号G06F13/42;

  • 国家 GB

  • 入库时间 2022-08-21 22:38:01

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