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System and method of efficiently implementing secure hash algorithm (SHA-1) in digital hardware that accomplishes optimal computation speed using minimal hardware resources
System and method of efficiently implementing secure hash algorithm (SHA-1) in digital hardware that accomplishes optimal computation speed using minimal hardware resources
A method of completing the Secure Hash Algorithm (SHA-1) computation in exactly 81 clock cycles with digital hardware. The general implementation techniques include: using a combination of synchronous storage elements to store the required computation values and asynchronous circuits to perform all the logic and mathematic operations of each step of the 81-step SHA-1 computation within a single clock cycle; using a quad-output-channel 16×32-bit circular queue memory to store the 512-bit message segment (block), as a computation buffer of the Wt parameter, and to supply the Wt-3, Wt-8, Wt-14, and Wt-16 data parameters simultaneously; using a combination of a counter circuit and a decoder/encoder circuit to control selecting data parameters and sequencing the 81-step SHA-1 computation; and using an automated controller to control internal units that perform SHA-1 and allowing external systems to access the SHA-1 computation service. The robust architecture allows for a highly efficient digital hardware implementation.
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机译:一种使用数字硬件在精确的81个时钟周期内完成安全哈希算法(SHA-1)计算的方法。通用的实现技术包括:使用同步存储元件组合存储所需的计算值,并使用异步电路在单个时钟周期内执行81步SHA-1计算的每个步骤的所有逻辑和数学运算;使用四路输出通道16 x 32位循环队列存储器来存储512位消息段(块),作为Wt参数的计算缓冲区,并提供Wt-3,Wt-8,Wt- 14,与Wt-16数据参数同时;使用计数器电路和解码器/编码器电路的组合来控制选择数据参数并对81步SHA-1计算进行排序;使用自动控制器来控制执行SHA-1的内部单元,并允许外部系统访问SHA-1计算服务。健壮的体系结构允许高效的数字硬件实现。
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