Lower power high speed design in BiCMOS processes

摘要

A low power high-speed design for integrated circuits using BiCMOS processes is disclosed. The design uses a first stage including bipolar transistor pairs configured as inputs and drivers for an output. A second CMOS stage is coupled to the first stage in a series-gated configuration and receives clock or data inputs. A third stage is coupled to the second stage and is configured as a current source. The combination results in circuits that can operate at conventional supply voltages of 1.8 volts.