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Systems and methods for timing a linear data path element during signal-timing verification of an integrated circuit design
Systems and methods for timing a linear data path element during signal-timing verification of an integrated circuit design
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机译:用于在集成电路设计的信号定时验证期间对线性数据路径元素进行定时的系统和方法
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摘要
Systems and methods for timing a linear data path element within an integrated circuit design are provided. A representative system includes a computer and a memory element associated with the computer. The computer includes logic for receiving information describing the integrated circuit design. The integrated circuit design includes a description of a signal-timing path and the clock distribution system across the integrated circuit. The memory is configured with executable steps to generate a model of a signal that traverses a signal-timing path that is coupled to a linear element. The model includes a mechanism for simulating clock signal operation over a plurality of clock distribution structure types. A representative method includes the following steps: acquiring circuit information; identifying a signal path within the circuit information; recognizing when the signal-timing path is coupled to a linear element; associating a clock uncertainty with the clock signal; determining a confidence interval for the signal-timing path responsive to the recognizing step, wherein the clock signal is propagated along the signal-timing path; and associating the confidence interval with the signal-timing path.
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