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Tailored barrier layer which provides improved copper interconnect electromigration resistance

机译:量身定制的阻挡层,可改善铜互连的电迁移电阻

摘要

Disclosed herein is a barrier layer structure useful in forming copper interconnects and electrical contacts of semiconductor devices. The barrier layer structure comprises a first layer of TaNx which is applied directly over the substrate, followed by a second layer of Ta. The TaNx/Ta barrier layer structure provides both a barrier to the diffusion of a copper layer deposited thereover, and enables the formation of a copper layer having a high 111 crystallographic content so that the electromigration resistance of the copper is increased. The TaNx layer, where x ranges from about 0.1 to about 1.5, is sufficiently amorphous to prevent the diffusion of copper into the underlying substrate, which is typically silicon or a dielectric such as silicon dioxide. The thickness of the TaNx and Ta layers used for an interconnect depend on the feature size and aspect ratio; typically, the TaNx layer thickness ranges from about 50 Å to about 1,000 Å, while the Ta layer thickness ranges from about 20 Å to about 500 Å. For a contact via, the permissible layer thickness on the via walls must be even more carefully controlled based on feature size and aspect ratio; typically, the TaNx layer thickness ranges from about 10 Å to about 300 Å, while the Ta layer thickness ranges from about 5 Å to about 300 Å. The copper layer is deposited at the thickness desired to suit the needs of the device. The copper layer may be deposited using any of the preferred techniques known in the art. Preferably, the entire copper layer, or at least a “seed” layer of copper, is deposited using physical vapor deposition techniques such as sputtering or evaporation, as opposed to CVD or electroplating. Since the crystal orientation of the copper is sensitive to deposition temperature, and since the copper may tend to dewet/delaminate from the barrier layer if the temperature is too high, it is important that the copper be deposited and/or annealed at a temperature of less than about 500° C., and preferably at a temperature of less than about 300° C.
机译:本文公开了用于形成铜互连和半导体器件的电接触的阻挡层结构。阻挡层结构包括直接施加在衬底上的第一层TaN x ,然后是第二层Ta。 TaN x / Ta阻挡层结构既为阻挡沉积在其上的铜层的扩散提供了阻挡,又使得能够形成具有高<111>晶体学含量的铜层,从而具有耐电迁移性。铜的增加。 TaN x 层,其中x的范围在大约0.1到大约1.5之间,是足够非晶的,以防止铜扩散到下面的衬底中,该衬底通常是硅或诸如二氧化硅的电介质。用于互连的TaN x 和Ta层的厚度取决于特征尺寸和长宽比。通常,TaN x 层的厚度在约50埃至约1000埃之间,而Ta层的厚度在约20埃至约500埃之间。对于接触通孔,必须根据特征尺寸和长宽比更仔细地控制通孔壁上的允许层厚度;通常,TaN x 层的厚度在约10埃至约300埃之间,而Ta层的厚度在约5埃至约300埃之间。铜层以适合器件需求的所需厚度沉积。可以使用本领域已知的任何优选技术来沉积铜层。优选地,与诸如CVD或电镀相反,使用诸如溅射或蒸发的物理气相沉积技术来沉积整个铜层或至少铜的“种子”层。由于铜的晶体取向对沉积温度敏感,并且如果温度过高,则铜可能会从势垒层中脱湿/脱层,因此重要的是,铜的沉积和/或退火温度应为200℃。小于约500℃,并且优选在小于约300℃的温度下。

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