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EXPLOITING SHORTEST PATH FOR IMPROVED NETWORK CLOCK DISTRIBUTION

机译:探索改善网络时钟分配的最短路径

摘要

It identifies short route, takes precedence over the delay transmission or the delay picture of the identical signal and, it offers the device and the method of utilizing the existence of short route with the transmission original (102) device and the intended (104) device by using the signal which takes short route, it improves the dispersion of the signal with that. This invention PLL from the signal which takes short route the phase detector (302) of the phase synchronous loop which mainly it selects drives offers the processor with the low-pass filters (304). In one execution form, the processor includes scaler such as the exponential scaler which offers the asymmetrically error weight attaching in order to improve the dispersion of the signal which accompanies small delay (shortly route).
机译:它识别短路径,优先于相同信号的延迟传输或延迟图像,并提供与传输原始(102)设备和预期(104)设备一起利用短路径存在的设备和方法通过使用短路径的信号,可以改善信号的色散。本发明的PLL从经过短路径的信号开始主要选择驱动的相位同步环路的相位检测器(302)为处理器提供低通滤波器(304)。在一种执行形式中,处理器包括缩放器,例如指数缩放器,该缩放器提供非对称误差权重附加,以改善伴随小延迟(短路径)的信号的色散。

著录项

  • 公开/公告号EP1593198A2

    专利类型

  • 公开/公告日2005-11-09

    原文格式PDF

  • 申请/专利权人 CIRRUS LOGIC INC.;

    申请/专利号EP20030796744

  • 发明设计人 GROSS KEVIN PAUL;

    申请日2003-11-25

  • 分类号H03D3/24;

  • 国家 EP

  • 入库时间 2022-08-21 22:06:34

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