首页> 外国专利> PCI BUS CONTROLLER HAVING SLAVE TEST BUS CONTROLLING FUNCTION BY INTEGRATING PCI BUS CONTROLLER CORE ANS TBC SLAVE CORE AS ONE CORE

PCI BUS CONTROLLER HAVING SLAVE TEST BUS CONTROLLING FUNCTION BY INTEGRATING PCI BUS CONTROLLER CORE ANS TBC SLAVE CORE AS ONE CORE

机译:通过将PCI总线控制器内核和TBC从机内核集成为一个内核,PCI总线控制器具有从站测试总线控制功能

摘要

PURPOSE: A PCI(Peripheral Component Interconnect) bus controller having a slave test bus controlling function is provided to perform the PCI bus control and the test bus control at the same time by integrating the PCI bus controller and an ASP(Address Scan Port). CONSTITUTION: A PCI bus controller block(10) includes a PCI bus controller core(11), a BSC(Boundary Scan Cell)(12), and a TAP(Test Access Port)(13). A back-end logic(200) connected to a single board(100) performs a specified process for general operations and gets to be a test board for the process when the test operation is performed. The PCI bus controller core controls communication between the back-end logic and other board or the processor connected to the PCI bus. A TBC(Test Bus Controller) slave core(20) enables the test by connecting the back-end logic with a TBC master. A board address setting part(300) comprises a dip switch or a jumper enabling the user to optionally select the board.
机译:目的:提供具有从属测试总线控制功能的PCI(外围组件互连)总线控制器,以通过集成PCI总线控制器和ASP(地址扫描端口)来同时执行PCI总线控制和测试总线控制。组成:PCI总线控制器模块(10)包括PCI总线控制器内核(11),BSC(边界扫描单元)(12)和TAP(测试访问端口)(13)。连接到单个板(100)的后端逻辑(200)执行用于一般操作的指定处理,并且在执行测试操作时成为该处理的测试板。 PCI总线控制器内核控制后端逻辑与连接到PCI总线的其他板或处理器之间的通信。 TBC(测试总线控制器)从属内核(20)通过将后端逻辑与TBC主控连接来启用测试。板地址设置部分(300)包括使用户能够可选地选择板的DIP开关或跳线。

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