首页> 外国专利> METHOD OF MANUFACTURING MOS TRANSISTOR WITH INCREASED CHANNEL WIDTH FOR INCREASING SIZE OF CHANNEL REGION WITHOUT INCREASE OF LINE WIDTH OF GATE ELECTRODE

METHOD OF MANUFACTURING MOS TRANSISTOR WITH INCREASED CHANNEL WIDTH FOR INCREASING SIZE OF CHANNEL REGION WITHOUT INCREASE OF LINE WIDTH OF GATE ELECTRODE

机译:在不增加栅极电极线宽的情况下制造具有增加的沟道宽度的MOS晶体管以增加沟道区域的尺寸的方法

摘要

PURPOSE: A method of manufacturing an MOS(Metal Oxide Semiconductor) transistor with an increased channel width is provided to improve electrical properties by increasing the size of a channel region without the increase of line width of a gate electrode using a trench. CONSTITUTION: Isolation layers(102) for defining an active region are formed in a semiconductor substrate(100). A well(104,106) is formed in the substrate of the active region. A trench is formed in the substrate along a channel length. A gate insulating layer(110) and a gate electrode(112) are sequentially formed along the substrate of the active region. A spacer made of an insulating layer is formed at both sidewalls of the gate electrode.
机译:目的:提供一种制造具有增加的沟道宽度的MOS(金属氧化物半导体)晶体管的方法,以通过增加沟道区域的尺寸而不增加使用沟槽的栅电极的线宽来改善电性能。构成:用于限定有源区的隔离层(102)形成在半导体衬底(100)中。在有源区的衬底中形成阱(104,106)。沿着沟道长度在衬底中形成沟槽。沿着有源区的衬底顺序地形成栅绝缘层(110)和栅电极(112)。由绝缘层制成的隔离物形成在栅电极的两个侧壁处。

著录项

  • 公开/公告号KR20050009512A

    专利类型

  • 公开/公告日2005-01-25

    原文格式PDF

  • 申请/专利权人 MAGNACHIP SEMICONDUCTOR LTD.;

    申请/专利号KR20030048845

  • 发明设计人 CHA JAE HAN;

    申请日2003-07-16

  • 分类号H01L21/336;

  • 国家 KR

  • 入库时间 2022-08-21 22:05:56

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