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SEMICONDUCTOR DEVICE HAVING WELL STRUCTURE FOR IMPROVING SOFT ERROR RATE IMMUNITY AND LATCH-UP IMMUNITY AND FABRICATION THE SAME
SEMICONDUCTOR DEVICE HAVING WELL STRUCTURE FOR IMPROVING SOFT ERROR RATE IMMUNITY AND LATCH-UP IMMUNITY AND FABRICATION THE SAME
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机译:具有改善软错误率抗扰性和闩锁抗扰性并制造相同结构的半导体器件
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摘要
A semiconductor device with improved soft error rate immunity and latch-up immunity and a method of forming the same. The device includes first wells of first conductivity type and second well of second conductivity type formed in the semiconductor substrate of first conductivity type. First conductivity type MOSFETs including source/drain of first conductivity type are formed in the second well, and second conductivity type MOSFETs including source/drain of second conductivity type in the first well. A third well of second conductivity type is formed at a region under the first wells and the drain of the second conductivity type MOSFETs. The first well is connected to the semiconductor substrate between the first well and the third well.
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