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Computer memory device with several random-access memory modules divided into disjunctive module groups each having memory cells organized in disjunctive cell groups with simultaneous write-in and read-out
Computer memory device with several random-access memory modules divided into disjunctive module groups each having memory cells organized in disjunctive cell groups with simultaneous write-in and read-out
The memory device has an even number of at least 4 random-access memory modules (D), each having a given number of memory cells organized in disjunctive cell groups, the cells in each group simultaneously selected by a cell group address for write-in or read-out of data via a m-bit data bus (DB), connected to an n-bit parallel port (DP) via a data register (DR). The memory modules are divided into at least 2 disjunctive module groups with the least possible difference in their spacings from the data register, a selection device (SR,DS,AB,A) used for selection of a module from the same module group for each m-bit group of the same n-bit packet.
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