One-time programmable memory device for integrated circuit, comprises floating gate formed over active area and isolation layer, inter-gate dielectric layer formed on floating gate, and control gate formed on inter-gate dielectric layer

摘要

A one-time programmable memory device comprises an isolation layer (105) for defining an active area of a substrate (100); an oxide layer formed on the active area; a floating gate (120a) formed over the active area and the isolation layer; an inter-gate dielectric layer (140a) formed on the floating gate; and a control gate (150a) formed on the inter-gate dielectric layer. Independent claims are also included for: (1) an integrated circuit (IC) comprising a memory device; a first transistor including a first gate, a first gate oxide layer interposed between the first gate and the substrate, and a first source region and a first drain region formed in the active area at least one of under and adjacent both sides of the first gate; and a second transistor including a second gate, a second gate oxide layer interposed between the second gate and the substrate, and a second source region and a second drain region formed in the active area at least one of under and adjacent both sides of the second gate; and (2) a method of fabricating IC, comprising forming isolation layers for defining a first and a second active area in a substrate; forming a tunnel oxide layer (115a) on the substrate; forming and patterning a floating gate material on a surface of the substrate including the tunnel oxide layer, to form a floating gate; forming an inter-gate dielectric layer including a composite layer having a silicon oxide layer and a silicon nitride layer, on a surface of the substrate including the floating gate; etching a portion of the inter-gate dielectric layer in the second active area to form a first gate oxide layer of a high voltage transistor, the first gate oxide layer being thicker than the tunnel oxide layer; forming and patterning a conductive material on a surface of the substrate including the inter-gate dielectric layer and the first gate oxide layer, to form a control gate and a first gate of the high voltage transistor; forming an interlayer insulating layer (170) comprising a contact hole on a resultant structure; and forming a metal interconnection (180) connectable to the control gate via the contact hole.