HARDWARE VERIFICATION PROGRAMMING LANGUAGE MODEL GENERATION APPARATUS, HARDWARE VERIFICATION PROGRAMMING LANGUAGE MODEL GENERATION METHOD, COMPUTER SYSTEM, HARDWARE SIMULATION METHOD, CONTROL PROGRAM, AND READABLE STORAGE MEDIUM

摘要

PPROBLEM TO BE SOLVED: To generate a verification model described in a general-purpose programming language capable of verifying hardware at a cycle accurate level at high speed and at low cost with a smaller amount of calculation as compared with a conventional art. PSOLUTION: A CDFG (control data flow graph) is generated from the operation description 107 of hardware is generated by a CDFG generation means 109, the CDFG is scheduled with an operating frequency required as hardware specifications and assigned for each state by a scheduling means 110, and the operating model of the hardware is generated as a description expressed in the general-purpose programming language for each state by a cycle accurate model generating means 111. The operating model of each node is generated by using operating information on nodes included in the CDFG and sequencing in calculating the operating model at each node by using connection information on the node is carried out. Thus, a model which can be simulated in each state can be generated. PCOPYRIGHT: (C)2006,JPO&NCIPI