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System on a chip having a system bus, an external bus, and a bus arbiter with programmable priorities for both buses, software, and method for assigning programmable priorities

机译:具有系统总线,外部总线和总线仲裁器的芯片上系统,该总线仲裁器具有总线的可编程优先级,软件和分配可编程优先级的方法

摘要

A system on a chip has functional blocks accommodated by at least one system bus, and an external bus for accommodating communication with external blocks. A single multi-jurisdictional bus arbiter has programmable rankings for assigning priorities to requests from blocks that are masters for either one of the both buses. Software and methods are also provided for assigning the priorities. The requests are analyzed with respect to which of the buses they require, and then priorities are assigned to maximize bus utilization, with increased speed for a system on a chip. In addition, a multi-jurisdictional multi-channel direct memory access block can be a master block for the system bus or the external bus.
机译:片上系统具有至少由一个系统总线容纳的功能块,以及用于容纳与外部块的通信的外部总线。单个多辖区总线仲裁器具有可编程的等级,用于将优先级分配给来自作为两种总线之一的主站的块的请求。还提供了用于分配优先级的软件和方法。根据请求所需的总线来分析请求,然后分配优先级以最大化总线利用率,同时提高片上系统的速度。另外,一个多辖区多通道直接存储器访问块可以是系统总线或外部总线的主块。

著录项

  • 公开/公告号US6976108B2

    专利类型

  • 公开/公告日2005-12-13

    原文格式PDF

  • 申请/专利权人 YOUNGSIK KIM;YUN-TAE LEE;

    申请/专利号US20010773874

  • 发明设计人 YOUNGSIK KIM;YUN-TAE LEE;

    申请日2001-01-31

  • 分类号G06F12/00;

  • 国家 US

  • 入库时间 2022-08-21 21:41:30

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