首页> 外国专利> Infinite field multiplying apparatus adapted for multiplying operation of GF3^m infinite field, mod 3 bit-stream adder therefor, and mod3 bit-stream adder therefor

Infinite field multiplying apparatus adapted for multiplying operation of GF3^m infinite field, mod 3 bit-stream adder therefor, and mod3 bit-stream adder therefor

机译:适用于GF3 ^ m个无限域的乘法运算的无限域乘法装置,其mod 3比特流加法器,及其mod3比特流加法器

摘要

The present invention relates to finite multiplication device as in particular, GF (3 ^ m) of a finite relates to a finite field multiplication unit for multiplication operation ; finite field multiplication unit according to the present invention, each of the multiplier and multiplicand input register for storing a count value of the multiplier and the multiplicand; Minimal polynomial coefficient register for storing values of minimum polynomials; Mod 3 bit multiplier that performs multiplication operations on the bit GF (3 ^ m) using the coefficients output from the multiplier and multiplicand input register; Using the intermediate calculation result and the output of the mod 3-bit multiplier to do the bit stream addition operation for GF (3 ^ m) mod 3-bit adder; Intermediate storage and operational results for the final output value stored in the output register; And GF (3 ^ m) finite field multiplication operation is characterized in that it comprises a controller for controlling so that the multiplication is carried out. ; finite field multiplication operation unit of GF (3 ^ m) in accordance with the present invention it is possible to perform the multiplication of the multiplier and multiplicand during m cycles that corresponds to the degree of the polynomial logic delay is not significant and have the binary finite field multiplication operations to obtain a similar performance effects.
机译:本发明涉及一种有限乘法器,特别是涉及一种有限域的GF(3 ^ m)涉及一种用于乘法运算的有限域乘法单元。根据本发明的有限域乘法单元,每个乘数和被乘数输入寄存器用于存储乘数和被乘数的计数值;最小多项式系数寄存器,用于存储最小多项式的值; Mod 3位乘法器,使用从乘法器和被乘数输入寄存器输出的系数对位GF(3 ^ m)进行乘法运算;使用中间计算结果和mod 3位乘法器的输出,对GF(3 ^ m)mod 3位加法器进行位流相加运算;最终输出值的中间存储和运算结果存储在输出寄存器中; GF(3 ^ m)有限域乘法运算的特征在于,它包括一个用于进行乘法控制的控制器。 ;根据本发明的GF(3 ^ m)的有限域乘法运算单元,有可能在m个周期内执行乘数和被乘数的乘法,这与多项式逻辑延迟的程度无关紧要并且具有二进制有限域乘法运算可以获得类似的性能效果。

著录项

  • 公开/公告号KR100550015B1

    专利类型

  • 公开/公告日2006-02-08

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20030093103

  • 发明设计人 최용제;김무섭;강주성;정교일;

    申请日2003-12-18

  • 分类号G06F7/52;

  • 国家 KR

  • 入库时间 2022-08-21 21:24:21

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