METHOD AND CIRCUIT TO INVESTIGATE CHARGE TRANSFER ARRAY TRANSISTOR CHARACTERISTICS AND AGING UNDER REALISTIC STRESS AND ITS IMPLEMENTATION TO DRAM MOSFET ARRAY TRANSISTOR

摘要

On determining the amount of charge transfer performance and the charge holding capacity of the DRAM cell transistor in the actual operating environment chip circuits and test methods are disclosed. It can be extended to evaluate the aging of the cell delivery apparatus due to the consumption MOSFET mechanism which is activated under the conditions for a method and circuit and the charge transfer operation or time. The on-chip circuitry allows, by force, and detects the voltage on the individual DRAM storage capacitor, can determine the charge transfer rate between the pulse test method determines the characteristics of the respective storage capacitor charge leakage, and the DRAM cell bit line and stored in the capacitor.