DUAL LAYER BUS ARCHITECTURE, SYSTEM-ON-A-CHIP HAVING THE DUAL LAYER BUS ARCHITECTURE AND METHOD OF ACCESSING THE DUAL LAYER BUS

摘要

A dual layer bus architecture for a system-on-a-chip (SOC) is disclosed. The bus architecture comprises a main bus adapted to connect a microprocessor, an image capture module, and a dual master module to a high density memory and a secondary memory operating independently of the main bus and adapted to connect the dual master module to a high-speed secondary memory.