Clock signal synchronizing device for use in e.g. double data rate-dynamic RAM of mobile telephone, has control device for activating and/or deactivating synchronizing device based on control signal that is evaluated by evaluating device

摘要

The device (101) has a delay mechanism with a variably controllable delay time (tvar) and into which a clock signal (CLK) is input and then issued as a delayed clock signal (DCLK). A phase comparator (104) compares the phase of the signal (CLK) with the phase of the signal (DCLK). A control device (116) for activating and/or deactivating the device (101) based on a control signal that is evaluated by an evaluating device. - An INDEPENDENT CLAIM is also included for method for synchronizing a clock signal.