Circuit arrangement for controllable delay of e.g. clock signals, in digital circuit, has two delay links with consecutively switched unidirectional delay units, and third delay link with set of switched unidirectional delay units

摘要

The arrangement has two delay links (KF, KG) with consecutively switched unidirectional delay units, and a third delay link with a set of consecutively switched unidirectional delay units. Each link is an active circuit with fixed throughput time, and the input of the delay units (F1) of the link (KF) is connected with a circuit input. The output of the delay units (G1) of the link (KG) is connected with a circuit output.