Pads layout structure for use in e.g. semiconductor memory component, has subsets of wire and non-wire bonding pads, where non-wire bonding pad subset is used to test component, while wire bonding pad subset is used for bonding component

摘要

The structure has subsets (PD501-PDn, PD502-PDn-1) of non-wire bonding and wire bonding pads, where the subset (PD502-PDn-1) of the non-wire bonding pad is used to test a semiconductor component, while the subset (PD501-PDn) of the wire bonding pad is used to bond the component. The non-wire bonding pad is designed such that it is electrically connected with a sensor top of a sensor card, while testing the component. An independent claim is also included for a layout method of pads.